Introduction
This paper discusses a robust algorithm to help application software enumerate the processor and cache topology in any single or multi-processor platform, using Intel processors. Enumerating processor topology correctly is essential for implementing licensing policy requirements. Understanding processor and cache topology information allows multithreading software to make more efficient use of hardware multithreading resources and deliver optimal performance.
Software must recognize hardware multi-processing support in all of these combinations. For licensing purposes, Intel recommends a policy based on discrete physical packages. For performance optimization purposes, software may need to manage physical resources depending on the details of the sharing topology implemented in these various forms of hardware multiprocessing.
We'll show how to detect the topological relationships between physical package, processor core, and logical processors sharing the same core in a multi-processing platform with IA-32 processors. The algorithm described applies across many hardware multi-processing configurations, including single-socket and multi-socket platforms, IA-32 processors supporting Hyper-Threading Technology, dual-core, and multiple cores.
Code Downloads: (Details about this code appear in the PDF, along with a full text listing of the source.)
View entire article [PDF 208KB]
