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Parallel programming has traditionally been considered using locks to synchronize concurrent access to shared data. Lock-based synchronization, however, has known pitfalls: using locks for fine-grain synchronization and composing code that already uses locks are both difficult and prone to deadlock. Transactional memory is proposed to simplify parallel programming by supporting “atomic” and “isolated” execution of user-specified tasks. It provides an alternate concurrency control mechanism that avoids these pitfalls and eases parallel programming. The Transactional memory C++ language constructs included opens the door for users to exercise the new language constructs for parallel programming, understand the transaction memory programming model, and provide feedback on the usefulness of these extensions with Intel C++ STM Compiler Prototype Edition. This posting includes the Intel® C++ STM Compiler Prototype Edition 2.0 and runtime libraries for Intel transactional memory language construct extensions.
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Flash Demo
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(1) A sample program in C++ with C++ virtual function using STM language extensions and OpenMP
Command Line:
Windows*: icl –Qtm_enabled –Qopenmp intel_stmtest_virtual.cpp –o virtual
./virtual.exe
Linux*: icc –Qtm_enabled –openmp intel_stmtest_virtual.cpp –o virtual
./virtual
(2) A sample program in C using STM language extensions and OpenMP
Command Line:
Windows*: icl –Qtm_enabled -Qstd=c99 –Qopenmp intel_stmtest_hashtable.c –o hashtable
./hashtable.exe 229 1000000 10000
Linux*: icc –Qtm_enabled –openmp intel_stmtest_hashtable.cpp –o hashtable
./hashtable 229 1000000 10000
Usage: hashtable [<size of hashtable> [<number of items> [<number of duplicates>]]]
size of hashtable : number of buckets
number of items: total number of items we try to insert and remove from the hashtable
number of duplicates: number of those items that are duplicates.
(3) A sample program in C using STM language extensions and pthreads on Linux*
Command Line:
Linux*: icc –Qtm_enabled –Wall intel_stmtest_counting.c –o counting -lpthread
./counting
intel_stmtest_counting.c
For the Windows version of this offering, you can find technical requirements here.
For the Linux version of this offering, technical requirements can be found here.
Q - What is new with Edition 2.0?
A - The Intel® C++ STM Compiler, Prototype Edition 2.0 for IA-32 and Intel®64
Q - What does STM stand for?
A - STM stands for Software Transactional Memory, a promising technology to help accelerate the creation of parallel applications. STM will benefit from additional real world testing and feedback to assist developers new to parallel programming.
Q - What are some of the prerequisites to using these extensions?
A - These extensions are for C and C++ programmers – on Windows and Linux, using Intel’s production compiler.
Q - Do I have to buy the Intel compiler to use these?
A - No you don't. You just need to make sure that you have an active license of the Intel(R) C++ Compiler for Windows or the Intel(R) C++ Compiler for Linux on your system. If you don't, you can easily acquire a commercial license or try an evaluation copy.
Q - What should I expect?
A - This is an ideal tool for general experimentation, testing and industry dialog around real results. It’s a great opportunity to explore Software Programming Models for parallel programming.
Q - How do I get support?
A - You are welcome to join our What If forum and post your question. The team will keep any eye on the discussion and do our best to answer your questions.
Q - What are the licensing terms that spell out how exactly I can use this utility?
A - The licensing terms are listed on the download page.
Robert Geva
Principal engineer at Intel’s software and solutions group. Robert joined Intel in 1991 and has since developed an expertise in compilers and performance analysis and tuning for microarchitectures. Robert has worked on compiler optimizations for a variety of Intel microprocessor based systems, including the 80486, the Pentium Processor, the Pentium Pro Processor, Itanium, the Pentium 4 and Pentium M. Robert is a SW architect within the Intel SW product division that is developing the transactional memory technology. Robert has BA and MSc from the Technion, Israel institute of technology
Ali-Reza Adl-Tabatabai
Senior Principal Engineer in Intel’s Programming Systems Lab. He leads a team of researchers working on compilers and scalable runtimes for future Intel Architectures. Ali has spent most of his career building high-performance programming language implementations, including static and dynamic optimizing compilers and language runtime systems. His current research concentrates on language features that make it easier for the mainstream developer to build reliable and scalable parallel programs for future multi-core architectures and on architectural support for those features. Most recently he has worked on transactional memory, a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. Ali has published over 20 papers in leading conferences and journals. He received his PhD in Computer Science from Carnegie Mellon University.
Xinmin Tian
Principal Engineer and Compiler Architect at Intel. Currently, he leads parallelization, OpenMP, vectoriztion and transactional memory development projects for Intel® C++/FORTRAN compilers for Intel® IA-32, Intel® 64, and Itanium® multi-core processors. He has over 30 refereed technical publications on compiler optimizations, parallel computing, and multithreaded architectures. Xinmin Tian is a coauthor of "The Software Optimization Cookbook" (Second Edition) at Intel Press published in 2006, and a main contributor for the "Multi-Core Programming" book published by Intel Press in 2006. Xinmin Tian holds a PHD in Computer Science and has 20 patents pending in the areas of compiler optimizations, parallelization, and multi-core architectures. He also served on program committees for research conferences and a referee for technical journals and conferences.
