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.NET
How-To
(14)
How to Apply Application-Level Tuning on the ASP.NET Platform
How to Apply System-Level Tuning on the ASP.NET Platform
How to Compile .java Files into .Net Executables
How to Convert Java .class Files to .NET Executables
How to Create & Version a .NET Assembly
How to Inspect the Internal Structure of a .NET Executable
How to Locate a .NET Assembly
How to Make a .NET Assembly Globally Accessible
How to Reference Java .class Files from a .NET Project
How to Share and Reference .NET Assemblies
How to Tune the MACHINE.CONFIG File on the ASP.NET Platform
How to Use a .NET Assembly
Optimize Applications on the ASP.NET Platform
Send Email from an ASP .NET Environment
Access to upcoming processors
How-To
(3)
Get Next-Generation Intel® Itanium® Processor-Based Systems
Schedule Exclusive Access
Test Your Software on the Intel® Itanium® Architecture
configuration
No Pages
Design superior apps
How-to
(4)
Initiate a Microsoft RTC Session in Windows XP
Integrate Real-Time Communications in Windows XP
Prepare for a Microsoft RTC Session in Windows XP
Process Microsoft RTC Session Data in Windows XP
Develop for Core processor
How-to
(5)
Algorithm Coding
(11)
Avoid Bottlenecks in Simple Math Functions
Establish Sound Coding Practices (Things to Do)
Explicit Prototyping for Floating-Point Functions
Get Faster Video Rendering on the Intel® Pentium® 4 Processor
Implement Software Exception Handling
Learn the 10 Most Important Technologies
Optimize Motion Compensation on the Pentium® 4 Processor
Optimize the AES Algorithm for the Intel® Pentium® 4 Processor
Sound Coding Practices (Things to Avoid)
Use Explicit Prototyping
Use the Microsoft C++ Compiler for the Pentium® M Processor
Coding
(2)
Support the CONTEXT Structure in Windows 2000 (64-bit)
Vectorize Code Using C/C++ Classes on 32-Bit Intel® Architecture
Data
(8)
Avoid Partial Memory Accesses on 32-Bit Intel® Architecture
Correct Endian Issues with Hex Constants Used as Byte Arrays
Loop Blocking to Optimize Memory Use on 32-Bit Architecture
Manage Structure Padding to Avoid Data Bloat
Manipulate Data Structure to Optimize Memory Use on 32-Bit Architecture
Manipulate Data Structure to Optimize Memory Use on 32-Bit Intel® Architecture
Replace a Set of Pointers With a Base Pointer to Reduce Data Bloat
Use Software Data Prefetch on 32-Bit Intel® Architecture
Instructions
(12)
Become Familiar with Streaming SIMD Extensions 3 Instructions
Implement a Horizontal Add/Subtract with SSE3 Instructions
Implement ADDSUBxx Streaming SIMD Extensions 3 Instructions
Implement Application Programming Model for Streaming SIMD Extensions 3 Instructions
Implement Streaming SIMD Extensions 3 Instructions Data-Movement Instructions
Implement the FISTTP Streaming SIMD Extensions 3 Instruction
Satisfy the System Programming Model for Streaming SIMD Extensions 3 Instructions
Switch between Instruction Types on 32-Bit Intel® Architecture
Use the MONITOR and MWAIT Streaming SIMD Extensions 3 Instructions
Vectorize Assembly Code by Hand on 32-Bit Intel® Architecture
Vectorize Code Automatically on 32-Bit Intel® Architecture
Vectorize Code Using Intrinsics on 32-Bit Intel® Architecture
Libraries
(10)
Create a UNIX (including Linux) Shared Library
Implement the LibM Math Library
Implement the Short Vector Math Library
Install a UNIX (including Linux) Shared Library
Link your Project to MKL libraries
Manage Versioning, Libraries, & Assemblies in Windows versus UNIX (including Linux)
Update a UNIX (including Linux) Shared Library
Use and Locate a UNIX (including Linux) Shared Library
Use Intriniscs
Vectorize Code on 32-Bit Intel® Architecture
Multi-Core
(2)
Algorithm Coding
(1)
TransCoding
Libraries
(2)
Math Kernel Libraries
Performance Libaries
SSE
(3)
16bit 3D Convolution: SSE4+OpenMP implementation on Penryn CPU
2x Shrink SSE algorithm
3D Running Average SSE algorithm
Glossary of Technical Terms
Parallel Programming & Multi-Core
(139)
Abstract data type
Abstraction
Address space
Amdahl's law
AND parallelism
Application Programming Interface
Atomic
Autoboxing
Bandwidth
Barrier
Beowulf cluster
Bi-section bandwidth
Bibliography
Broadcast
Bus architecture
Cache
ccNUMA
Cluster
Collective communication
Concurrent execution
Concurrent program
Condition variable
Contention
Copy on write
Core
Counting semaphore
Critical section
Cyclic distribution
Data parallel
Deadlock
Design pattern
Distributed computing
Distributed shared memory
DSM
Eager evaluation
Efficiency
Embarrassingly parallel
EPIC
Explicitly parallel language
Factory
False sharing
Fence
Fork
Fork/join
Framework
Future variable
Generic programming
Generics
Grid
Heterogeneous
Homogeneous
Hypercube
Implicitly parallel language
Incremental parallelism
Java
Java Virtual Machine
Join
JVM
Latency
Lazy evaluation
Linda
Live lock
Load balance
Load balancing
Locality
Lock
Many-core processor
Massively parallel processor
Master/Worker
MESI protocol
Message Passing Interface
MIMD
Monitor
MPI*
MPP
Multi-core processor
Multicomputer
Multiprocessor
Mutex
Node
NUMA
OpenMP*
OR parallelism
Parallel file system
Parallel overhead
PE
Peer-to-peer computing
Point-to-point architecture
Polymorphism
POSIX
Precedence graph
Process
Process migration
Processing element
Programming environment
Programming model
Pthreads
PVM
Race condition
Reader/writer locks
Reduction
Refactoring
Remote procedure call
RPC
Semaphore
Serial fraction
Server/workstation farm
Shared address space
Shared memory
Shared nothing
SIMD
Simultaneous multithreading
Single Program Multiple Data
Single-assignment variable
SMP
SMT
Snoop filter
Snooping
Speedup
SPMD
Stride
Strongly ordered memory
Symmetric multiprocessor
Synchronization
Systolic algorithm
Systolic array
Task
Task Parallelism
Task queue
Thread
Thread pool
Transputer
Tuple space
UE
Unit of execution
Vector supercomputer
Virtual shared memory
Virtual shared memory
Weakly ordered memory
Graphics
General
(1)
Custom Resolutions on Intel Graphics
High Performance Computing
How-To
(4)
Build a Linux HPC Cluster with Itanium®-Based Systems
Correct Number of Nodes for an HPC Cluster
Determine the Correct Interconnect Technology for an HPC Cluster
Determining whether HPC Cluster Should Be 32-Bit or 64-Bit Processors
LCD vectorization + threading benchmark
Performance implications of MATMUL and MKL BLAS substitutions in Polyhedron benchmarks
Itanium
How-to
(9)
64-bit Coding
(12)
Access a 32-Bit DLL from a Native 64-Bit Process on Intel Architecture
Avoid Memory-Coding Errors on 64-Bit Intel® Architecture
Ensure that the 64-Bit Compiler Can Find Type Mismatches
Handle Win64 Errors Related to Obsolete Win32 Constants
Handle Win64 printf or wsprintf Warnings
Handle Win64 Truncation Warnings
Manage Thread-Stack Size in 64-bit UNIX
Manage Thread-Stack Size in Windows 2000 (64-bit)
Select a Win64 Porting Model
Support Hex Constants on 64-Bit Intel Architecture
Use Appropriate Data Types to Manage 64-bit Data Size
Use Make files to Resolve Win64 Porting Issues
Compiler
(6)
Guide Compilers to Optimize Inner Loops for 64-Bit Intel Architecture
Guide Compilers to Optimize Inner Loops for 64-Bit Intel Architecture
Improve Performance on 64-Bit Intel Architecture with Intel C++ Compiler for Linux Options
Resolve Cache Misses on 64-Bit Intel Architecture
Use Intel Compilers Successfully for 64-Bit Intel Architecture
Use Pragmas with the Intel® C++ Compiler for Linux on 64-Bit Architecture
DB2
(8)
Allocate Memory Optimally to the Bufferpool and Sortheap for DB2 Databases on Itanium-Based Systems
Configure Striping Size and Eventsize for IBM DB2 Databases on Itanium-Based Systems
Define Tablespaces Properly for IBM DB2 Databases on Itanium® 2-Based Systems
Divide the IBM DB2 Database Workload among Itanium® Processors
Measure Performance of IBM DB2 Databases on Itanium®-Based Systems
Optimally Define IBM DB2 Bufferpool Page Size for Itanium-Based Systems
Set Prefetch Size Optimally for IBM DB2 Databases on Itanium®-Based Systems
Tune IBM DB2 Databases for Performance on Itanium®-Based Systems
Itanium Coding
(11)
Develop Coding Best Practices Targeting Compilers for 64-Bit Intel® Architecture
Explicit Bundles in Assembly Code for 64-Bit Architecture
Implement Efficient MADD Operations on 64-Bit Intel Architecture
Implement Efficient MADD Operations on 64-Bit Intel® Architecture
Include Optimized Assembly Code in Compilation for 64-Bit Intel® Architecture
Locate Code in Assembly Language for 64-Bit Intel® Architecture
Manage Jump Buffer Size for Itanium Architecture
Support Integer-Constant-Type Suffixes on 64-Bit Architecture
Trace the Logic in an Assembly Code Listing for 64-Bit Intel Architecture
Use Code from the Intel® Itanium Processor on the Itanium 2 Processor
Use Code Guards to Compile 32-bit Code for the Itanium Architecture
Libraries
(1)
Use Intel Performance Libraries on 64-Bit Architecture
Memory Access
(8)
Ensure Accurate Data Access When Using An Offset with Itanium Architecture
Identify Bank/Address Conflicts on 64-Bit Intel Architecture
Quantify Integer Bank-Conflict Penalties on 64-Bit Intel Architecture
Remove Many Bank Conflicts on 64-Bit Intel® Architecture
Remove Many Bank Conflicts on 64-Bit Intel® Architecture
Resolve Address Conflicts on 64-Bit Architecture
Resolve Data-Alignment Errors for the Itanium Architecture
Short Data Segment Overflow Errors on 64-Bit Architecture
Performance
(19)
Analyze Memory Accesses on 64-Bit Intel Architecture
Code Timing and Profiling for Linux on 64-Bit Intel® Architecture
Develop an Execution-Time Benchmark on 64-Bit Intel Architecture
Handle Streaming Data Optimally on 64-Bit Architecture
Identify Back-End Bubbles on 64-Bit Intel® Architecture
Identify Branch Misprediction on 64-Bit Intel Architecture
Improve Code Based on Root-Cause Analysis on 64-Bit Intel® Architecture
Improve Performance on 64-Bit Architecture of Applications with Many Small Functions
Improve Performance on 64-Bit Architecture of Applications with Many Small Functions
Increase the Frequency of First-Level Instruction-Cache Hits on 64-Bit Intel Architecture
Instruction Latencies in Assembly Code for 64-Bit Intel® Architecture
Perform Back-End Bubble Root-Cause Analysis on 64-Bit Intel® Architecture
Perform Code Timing and Profiling for Linux on 64-Bit Architecture
Prepare Applications for Optimization on 64-Bit Intel® Architecture
Prioritize Bottlenecks on the Itanium Processor
Quantify Floating-Point Bank-Conflict Penalties on 64-Bit Intel Architecture
Quantify the Penalty of Branch Misprediction on 64-Bit Architecture
Resolve Back-End Bubbles on 64-Bit Intel® Architecture
Schedule Instructions Optimally on 64-Bit Intel® Architecture
Porting
(2)
Develop Linux Applications for Compatibility between Itanium-Based Systems and the IBM POWER architecture
Port Linux Applications
Stall Analysis
(9)
Analyze Bottlenecks from 64-bit Pipeline Stalls at the DET Stage
Analyze Pipeline Flush Losses on 64-Bit Intel Architecture
Analyze Pipeline Stalls on 64-Bit Intel Architecture
Characterize Application Performance with Stall Events on 64-Bit Architecture
Functional Unit Stalls on 64-Bit Intel® Architecture
Quantify Memory-Stall Penalties on 64-Bit Architecture
Register-Stack Engine Stalls on 64-Bit Architecture
Resolve Memory Access Stalls on 64-Bit Intel® Architecture
Use Stall Events to Identify Optimization Opportunities on 64-Bit Architecture
Linux
memcpy performance
Red Hat EL5 x86-64 installation
Manageability
FAQ for Intel® Active Management Technology Management Pack 3.0 for Ops Mgr/Essentials
Frequently Asked Questions
(2)
FAQs: Intel® AMT Setup and Configuration Service (SCS)
FAQs: Intel® AMT Software Development Kit (SDK)
(4)
Debugging
Deployment
Functionality
General
Top development challenges with Intel(R) AMT & suggestions
Mobility
Experience in mobilizing apps
General
(4)
Access to a Camera
Best Use of Available Memory on Handheld Devices
Calculate the Clock Speed of a Mobile Processor
PXA9xx / PXA27x / XScale -- How to get developer support
How-To
(7)
Application Development
(8)
Add Mobility Requirements to the Software Development Life Cycle
Build Cross-Platform Mobilized Applications
Business case for mobilized solutions
Determine the Scope of a Software Mobilization Project
Formulate a Business Case for Deploying Mobilized Solutions
Mobilize Software Applications
Use Intelligent Documents as Enterprise Front-Ends
Use intelligent documents as enterprise front-ends
How to Store and Retrieve Data From Cookies
(1)
Looking For an API to Detect Radio Off Condition for Centrino WLANs
Mobile Intel® Core™2 Processor Detection Table
Mobile Power Management Tool
Network Aware
(16)
Address Changes in Network State in Mobilized Software
Address changes in network state in mobilized software
Address Connectivity State in Mobilized Software
Changes in Effective Data-Transfer Rate in Mobilized .NET Applications
Changes in Target Machine Visibility in Mobilized .NET* Applications
Detect Internet Connectivity for a Handheld
Determine Target Machine Visibility in Mobilized .NET* Applications
Determine Which Connection a Mobilized Application Will Use
Effective Data-Transfer Rate in Mobilized .NET* Applications
Monitor Network Connection Status Using .NET and Web Services
Network Detection for Mobility
Network Outages in Mobilized Applications
Return Network Adaptor Information for a Handheld
Roam seamlessly between WiFi Hotspots and 2.5 or 3G networks
Use Microsoft SENS for Network Detection
Write a Custom Implementation for Network Detection
Off-line Synchronization
(6)
Create an ADO.NET DataSet for a Mobilized Application
Make Local Changes to an ADO.NET DataSet in a Mobilized Application
Manipulate Data in an ADO.NET DataSet in a Mobilized Application
Secure Mobilized Applications and Wireless Clients
Support Dynamic Content in an Offline Context
Track Changes to an ADO.NET DataSet in a Mobilized Application
Security
(7)
Identify Mobile Platform Security Threats
Help Secure PDAs against Misuse
Mobile Device Vulnerability Database (MDVD)
Network Security Remedies to Secure Mobile Communications
Secure Mobilized Software
Secure PDAs Using Hardware Features
Secure PDAs Using Software Features
Mobilization Issues Associated with Terminal Emulation
Multi-thread apps for Multi-core
Experience in threading
How to thread?
(5)
Analysis
(9)
Analysis Phase of Threaded Application Development Cycle
Apply Data Decomposition to Create Threaded Code
Apply Functional Decomposition to Improve Efficiency of Input/Output Operations
Choose the Right Threading Model (Task-Parallel or Data-Parallel Threading)
Debugging & Testing Phase of Threaded Application Development
Implement Threading in a Data-Decomposition Problem
Structure the Design Phase of Threaded Application Development Cycle
Structure the Implementation Phase of Threaded Application Development
Tuning Phase of Threaded Application Development
Design
(4)
Divide Work among Multiple Threads in a .NET Web Service Client
Implement Threading in a Functional-Decomposition Problem
Performance Degradation Due to Spin-Wait Loops on Hyper-Threading Technology-Enabled Systems
Resolve Memory Conflicts in Data-Decomposition Problems
Performance analysis
(7)
Detect Stalls Due to Exceeding Write-Combining Store Buffers on Hyper-Threading Technology-Enabled Systems
False Sharing
Isolate Application Performance Issues on Hyper-Threading Technology-Enabled Systems
Memory Conflicts in Functional-Decomposition Problems
Performance in Threaded Applications Using the Intel® VTune™ Performance Analyzer
Processor Time Counter to Evaluate Threading Methodology
Use Instructions Retired Events to Evaluate Threading Methodology
Programming
(7)
Best Threading Model for You
Express Data Parallelism (with OpenMP* and Intel® Compilers) without large scale modifications to serial code
Manage Complexity when Threading a .NET Web Service Client
Managed Runtime Threading - Best Practices
Number of Logical Processors per Physical Processor
Test DLLs for Thread Safety
Transfer Control among Threads in a .NET Web Service Client
Synchronization
(6)
Avoid Excessive Synchronization
Perform Synchronization Using Thread Locking
Synchronization (Avoiding Race Conditions) without Blocking Threads
Use Win32 Functions to Manage Event Objects
Win32 Functions to Create, Suspend, and Terminate Threads
Win32 Functions to Manage Semaphores
Hyper-Threading
(10)
Avoid Resource Contention on Hyper-Threading Technology-Enabled Systems
Cache Block Size on Processors that Support Hyper-Threading Technology
Cache Block Size on Processors without Hyper-Threading Technology
Cache Effects on Applications Running on Hyper-Threading Technology-Enabled Processors
Effectiveness of Hyper-Threading Technology With an Application
Multi-core Introduction
Performance Issues on Hyper-Threading Technology-Enabled Systems
Processing Loads on Systems with Hyper-Threading Technology
Resolve 64K Alias Conflicts on Hyper-Threading Technology-Enabled Systems
Write-Combining Store Buffers on Hyper-Threading Technology-Enabled Systems
Reference threaded apps
(4)
Desktop search
Download manager
FTP client
XNA* game
References
Threaded Code Examples
(6)
AE provided
From online books
Open source samples
OpenMP
Threading building blocks
(9)
All facilities - Fibonacci
Concurrent hash map
Parallel for
Parallel for -Tachyon
Parallel reduce
Parallel while
Pipeline
Substring finder
Task - tree sum
TopCoder* contests
(9)
BoxPacking
CentrallyLocated
MessageReceiver
NearestNeighbors
PartitionGraph
Polyminoes
RoutePackets
StringSearch
Sudoku
Threading case studies
Threading tools
(3)
Development of Threaded Applications
Thread Checker
ThreadProfiler
Performance optimization
Compiler
(1)
Use Intel Compilers with Intel NetBurst Microarchitecture
Execution
(7)
De-Pipelining Performance Issues on 32-Bit Intel® Architecture
Excess Riscification on the Pentium® 4 Processor
Optimize Code for the Most-Often Used Code Path
Schedule Processing Loads on Dual-Processor Systems
Source-Level Optimizations for the Pentium® M Processor
Store-Forwarding Stalls on the Pentium® 4 Processor
Unpredictable Conditional Branches on 32-Bit Intel® Architecture
Floating point
(2)
Floating-Point Performance and Vectorization
Performance Penalties for Gradual-Underflow Behavior
How-To
(1)
Memory, cache
(14)
Align and Organize Data for Better Performance
Align Data Structures on Cache Boundaries
Cache Size on Pentium® M Processors
Cache Splits with Streaming SIMD Extensions 3 Instructions
Choose between Hardware and Software Prefetch on 32-Bit Intel® Architecture
Create Cache-Data Blocks
Data Alignment on 32-Bit Intel® Architecture
Data-Access Pattern Alignment & Contiguity on 32-Bit Intel® Architecture
Deswizzle Data from SoA Format to AoS
Latency of Floating Point-to-Integer Conversions
Optimize Prefetch on 32-Bit Intel® Architecture
Reduce the Impact of Misaligned Memory Accesses
Solve Prefetch Performance Issues
Strip Mining to Optimize Memory Use on 32-Bit Intel® Architecture
VTune
(4)
Best Use of the Intel® VTune™ Performance Analyzer
Use the VTune™ Performance Analyzer to Track Down Overhead
Vtune Performance Analyzer
VTune™ Performance Analyzer to Detect Idle Time
Power efficiency
.NET Monitor Power Status
Conserve Power in Mobilized Software
Extend battery life
How-To
(2)
Power-Aware Mobilized Windows Applications
Use Windows XP Power-Event Interception and Control
Linux Laptop Power Management
Low Power Intel® Architecture for Small Form Factor Devices: Supplemental Information
Media apps
PeekMessage Calls in Mobilized Applications
Power Consumption in Real-Time Threaded Application
Prevent System from Transitioning to Sleep Mode
Sleep/Wake transitions
Processor feature detection
Associate Logical Processors to Physical Processors
Backward Compatibility of an Application
Characteristics of 32-Bit IA Processors
Feature detection API
How-To
(1)
Backward Compatibility of an Application
Multi-core detect
Pentium M Processor
Processor Supports of Hyper-Threading Technology
Retrieve the Processor APIC ID
Software Certification
Certified Solutions Program
How-to
(1)
How do I contact Technical Support?
VT - Virtualization
Digital home
(3)
‘Appliance’ Model in the Digital Home
Digital Home Security with VT
Expand Digital Home Functionality with VT
Digital office
(1)
Implement Intel VT on Digital Office Desktops
How-To
(2)
Digital Office
(2)
Implement Intel® VT in the Digital Office
Implement on Digital Office Servers
Investigate the Intel® Virtualization Technology Ecosystem
Incorporate VT with IA-32 Architecture
Incorporate VT with Itanium Architecture
Investigate the Intel® Virtualization Technology Ecosystem
Limitations of Software-Based VT
Network Interface Card (NIC) Requirements
Software Requirements for a VMware VT Solution
Software-Based Virtualization
Technical Information about Intel VT
Usage models
(11)
Benefits of Intel VT
Develop Usage Models for Intel® VT
Hardware Total Cost of Ownership with VT
Hide Hardware Complexity
Innovative usage models
Mobile Productivity with VT
Non-Hardware Costs with VT
Scale Large Compute Problems to Multiple Computers Using VT
Set Goals for VT
Simplify PC Updates
Users Have Custom Experience on Any Computer
Virtualization in the Digital Office
VT Challenges with VT-x and VT-i
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